Constantsยง
- MSR_
AMD64_ BU_ CFG2 - MSR_
AMD64_ CPUID_ FN_ 1 - MSR_
AMD64_ DC_ CFG - MSR_
AMD64_ DE_ CFG - MSR_
AMD64_ DE_ CFG_ LFENCE_ SERIALIZE_ BIT - MSR_
AMD64_ DE_ CFG_ ZEN2_ FP_ BACKUP_ FIX_ BIT - MSR_
AMD64_ IBSBRTARGET - MSR_
AMD64_ IBSCTL - MSR_
AMD64_ IBSDCLINAD - MSR_
AMD64_ IBSDCPHYSAD - MSR_
AMD64_ IBSFETCHCTL - MSR_
AMD64_ IBSFETCHLINAD - MSR_
AMD64_ IBSFETCHPHYSAD - MSR_
AMD64_ IBSFETCH_ REG_ COUNT - MSR_
AMD64_ IBSFETCH_ REG_ MASK - MSR_
AMD64_ IBSOPCTL - MSR_
AMD64_ IBSOPDATA - MSR_
AMD64_ IBSOPDAT A2 - MSR_
AMD64_ IBSOPDAT A3 - MSR_
AMD64_ IBSOPDAT A4 - MSR_
AMD64_ IBSOPRIP - MSR_
AMD64_ IBSOP_ REG_ COUNT - MSR_
AMD64_ IBSOP_ REG_ MASK - MSR_
AMD64_ IBS_ REG_ COUNT_ MAX - MSR_
AMD64_ ICIBSEXTDCTL - MSR_
AMD64_ LBR_ SELECT - MSR_
AMD64_ LS_ CFG - MSR_
AMD64_ MC0_ MASK - MSR_
AMD64_ NB_ CFG - MSR_
AMD64_ OSVW_ ID_ LENGTH - MSR_
AMD64_ OSVW_ STATUS - MSR_
AMD64_ PATCH_ LEVEL - MSR_
AMD64_ PATCH_ LOADER - MSR_
AMD64_ PERF_ CNTR_ GLOBAL_ CTL - MSR_
AMD64_ PERF_ CNTR_ GLOBAL_ STATUS - MSR_
AMD64_ PERF_ CNTR_ GLOBAL_ STATUS_ CLR - MSR_
AMD64_ RMP_ BASE - MSR_
AMD64_ RMP_ END - MSR_
AMD64_ SEV - MSR_
AMD64_ SEV_ ENABLED_ BIT - MSR_
AMD64_ SEV_ ES_ ENABLED_ BIT - MSR_
AMD64_ SEV_ ES_ GHCB - MSR_
AMD64_ SEV_ SNP_ ENABLED_ BIT - MSR_
AMD64_ SNP_ ALT_ INJ_ BIT - MSR_
AMD64_ SNP_ BTB_ ISOLATION_ BIT - MSR_
AMD64_ SNP_ DEBUG_ SWAP_ BIT - MSR_
AMD64_ SNP_ IBS_ VIRT_ BIT - MSR_
AMD64_ SNP_ PREVENT_ HOST_ IBS_ BIT - MSR_
AMD64_ SNP_ REFLECT_ VC_ BIT - MSR_
AMD64_ SNP_ RESTRICTED_ INJ_ BIT - MSR_
AMD64_ SNP_ RESV_ BIT - MSR_
AMD64_ SNP_ SECURE_ TSC_ BIT - MSR_
AMD64_ SNP_ SMT_ PROT_ BIT - MSR_
AMD64_ SNP_ VMGEXIT_ PARAM_ BIT - MSR_
AMD64_ SNP_ VMPL_ SSS_ BIT - MSR_
AMD64_ SNP_ VMSA_ REG_ PROT_ BIT - MSR_
AMD64_ SNP_ VTOM_ BIT - MSR_
AMD64_ SVM_ AVIC_ DOORBELL - MSR_
AMD64_ SYSCFG - MSR_
AMD64_ SYSCFG_ MEM_ ENCRYPT_ BIT - MSR_
AMD64_ SYSCFG_ MFDM_ BIT - MSR_
AMD64_ SYSCFG_ SNP_ EN_ BIT - MSR_
AMD64_ SYSCFG_ SNP_ VMPL_ EN_ BIT - MSR_
AMD64_ TSC_ RATIO - MSR_
AMD64_ TW_ CFG - MSR_
AMD64_ VIRT_ SPEC_ CTRL - MSR_
AMD64_ VM_ PAGE_ FLUSH - MSR_
AMD_ CORE_ ENERGY_ STATUS - MSR_
AMD_ CPPC_ CAP1 - MSR_
AMD_ CPPC_ CAP2 - MSR_
AMD_ CPPC_ ENABLE - MSR_
AMD_ CPPC_ REQ - MSR_
AMD_ CPPC_ STATUS - MSR_
AMD_ DBG_ EXTN_ CFG - MSR_
AMD_ PERF_ CTL - MSR_
AMD_ PERF_ STATUS - MSR_
AMD_ PKG_ ENERGY_ STATUS - MSR_
AMD_ PPIN - MSR_
AMD_ PPIN_ CTL - MSR_
AMD_ PSTATE_ DEF_ BASE - MSR_
AMD_ RAPL_ POWER_ UNIT - MSR_
AMD_ SAMP_ BR_ FROM - MSR_
ARCH_ LBR_ CTL - MSR_
ARCH_ LBR_ DEPTH - MSR_
ARCH_ LBR_ FROM_ 0 - MSR_
ARCH_ LBR_ INFO_ 0 - MSR_
ARCH_ LBR_ TO_ 0 - MSR_
ATOM_ CORE_ RATIOS - MSR_
ATOM_ CORE_ TURBO_ RATIOS - MSR_
ATOM_ CORE_ TURBO_ VIDS - MSR_
ATOM_ CORE_ VIDS - MSR_
ATOM_ PKG_ C6_ RESIDENCY - MSR_
CC6_ DEMOTION_ POLICY_ CONFIG - MSR_
CONFIG_ TDP_ CONTROL - MSR_
CONFIG_ TDP_ LEVEL_ 1 - MSR_
CONFIG_ TDP_ LEVEL_ 2 - MSR_
CONFIG_ TDP_ NOMINAL - MSR_
CORE_ C1_ RES - MSR_
CORE_ C3_ RESIDENCY - MSR_
CORE_ C6_ RESIDENCY - MSR_
CORE_ C7_ RESIDENCY - MSR_
CORE_ PERF_ FIXED_ CTR0 - MSR_
CORE_ PERF_ FIXED_ CTR1 - MSR_
CORE_ PERF_ FIXED_ CTR2 - MSR_
CORE_ PERF_ FIXED_ CTR3 - MSR_
CORE_ PERF_ FIXED_ CTR_ CTRL - MSR_
CORE_ PERF_ GLOBAL_ CTRL - MSR_
CORE_ PERF_ GLOBAL_ OVF_ CTRL - MSR_
CORE_ PERF_ GLOBAL_ OVF_ CTRL_ COND_ CHGD - MSR_
CORE_ PERF_ GLOBAL_ OVF_ CTRL_ COND_ CHGD_ BIT - MSR_
CORE_ PERF_ GLOBAL_ OVF_ CTRL_ OVF_ BUF - MSR_
CORE_ PERF_ GLOBAL_ OVF_ CTRL_ OVF_ BUF_ BIT - MSR_
CORE_ PERF_ GLOBAL_ OVF_ CTRL_ TRACE_ TOPA_ PMI - MSR_
CORE_ PERF_ GLOBAL_ OVF_ CTRL_ TRACE_ TOPA_ PMI_ BIT - MSR_
CORE_ PERF_ GLOBAL_ STATUS - MSR_
CORE_ PERF_ LIMIT_ REASONS - MSR_
CSTAR - MSR_
DRAM_ ENERGY_ STATUS - MSR_
DRAM_ PERF_ STATUS - MSR_
DRAM_ POWER_ INFO - MSR_
DRAM_ POWER_ LIMIT - MSR_
EBC_ FREQUENCY_ ID - MSR_
EFER - MSR_
ERROR_ CONTROL - MSR_
F15H_ CU_ MAX_ PWR_ ACCUMULATOR - MSR_
F15H_ CU_ PWR_ ACCUMULATOR - MSR_
F15H_ EX_ CFG - MSR_
F15H_ IC_ CFG - MSR_
F15H_ NB_ PERF_ CTL - MSR_
F15H_ NB_ PERF_ CTR - MSR_
F15H_ PERF_ CTL - MSR_
F15H_ PERF_ CTL0 - MSR_
F15H_ PERF_ CTL1 - MSR_
F15H_ PERF_ CTL2 - MSR_
F15H_ PERF_ CTL3 - MSR_
F15H_ PERF_ CTL4 - MSR_
F15H_ PERF_ CTL5 - MSR_
F15H_ PERF_ CTR - MSR_
F15H_ PERF_ CTR0 - MSR_
F15H_ PERF_ CTR1 - MSR_
F15H_ PERF_ CTR2 - MSR_
F15H_ PERF_ CTR3 - MSR_
F15H_ PERF_ CTR4 - MSR_
F15H_ PERF_ CTR5 - MSR_
F15H_ PTSC - MSR_
F16H_ DR0_ ADDR_ MASK - MSR_
F16H_ DR1_ ADDR_ MASK - MSR_
F16H_ DR2_ ADDR_ MASK - MSR_
F16H_ DR3_ ADDR_ MASK - MSR_
F16H_ L2I_ PERF_ CTL - MSR_
F16H_ L2I_ PERF_ CTR - MSR_
F17H_ IRPERF - MSR_
F19H_ UMC_ PERF_ CTL - MSR_
F19H_ UMC_ PERF_ CTR - MSR_
FAM10H_ MMIO_ CONF_ BASE - MSR_
FAM10H_ NODE_ ID - MSR_
FSB_ FREQ - MSR_
FS_ BASE - MSR_
GEODE_ BUSCONT_ CONF0 - MSR_
GFX_ PERF_ LIMIT_ REASONS - MSR_
GS_ BASE - MSR_
HWP_ CAPABILITIES - MSR_
HWP_ INTERRUPT - MSR_
HWP_ REQUEST - MSR_
HWP_ REQUEST_ PKG - MSR_
HWP_ STATUS - MSR_
IA32_ APERF - MSR_
IA32_ APICBASE - MSR_
IA32_ APICBASE_ BASE - MSR_
IA32_ APICBASE_ BSP - MSR_
IA32_ APICBASE_ ENABLE - MSR_
IA32_ ARCH_ CAPABILITIES - MSR_
IA32_ BBL_ CR_ CTL - MSR_
IA32_ BBL_ CR_ CTL3 - MSR_
IA32_ BNDCFGS - MSR_
IA32_ BNDCFGS_ RSVD - MSR_
IA32_ CORE_ CAPS - MSR_
IA32_ CORE_ CAPS_ INTEGRITY_ CAPS_ BIT - MSR_
IA32_ CORE_ CAPS_ SPLIT_ LOCK_ DETECT_ BIT - MSR_
IA32_ CR_ PAT - MSR_
IA32_ DEBUGCTLMSR - MSR_
IA32_ DS_ AREA - MSR_
IA32_ EBL_ CR_ POWERON - MSR_
IA32_ ENERGY_ PERF_ BIAS - MSR_
IA32_ EVT_ CFG_ BASE - MSR_
IA32_ FEAT_ CTL - MSR_
IA32_ FLUSH_ CMD - MSR_
IA32_ FRED_ CONFIG - MSR_
IA32_ FRED_ RSP0 - MSR_
IA32_ FRED_ RSP1 - MSR_
IA32_ FRED_ RSP2 - MSR_
IA32_ FRED_ RSP3 - MSR_
IA32_ FRED_ SSP1 - MSR_
IA32_ FRED_ SSP2 - MSR_
IA32_ FRED_ SSP3 - MSR_
IA32_ FRED_ STKLVLS - MSR_
IA32_ HW_ FEEDBACK_ CONFIG - MSR_
IA32_ HW_ FEEDBACK_ PTR - MSR_
IA32_ INT_ SSP_ TAB - MSR_
IA32_ L2_ CBM_ BASE - MSR_
IA32_ L2_ QOS_ CFG - MSR_
IA32_ L3_ CBM_ BASE - MSR_
IA32_ L3_ QOS_ CFG - MSR_
IA32_ LASTBRANCHFROMIP - MSR_
IA32_ LASTBRANCHTOIP - MSR_
IA32_ LASTINTFROMIP - MSR_
IA32_ LASTINTTOIP - MSR_
IA32_ MBA_ BW_ BASE - MSR_
IA32_ MBA_ THRTL_ BASE - MSR_
IA32_ MC0_ ADDR - MSR_
IA32_ MC0_ CTL - MSR_
IA32_ MC0_ CTL2 - MSR_
IA32_ MC0_ MISC - MSR_
IA32_ MC0_ STATUS - MSR_
IA32_ MCG_ CAP - MSR_
IA32_ MCG_ CTL - MSR_
IA32_ MCG_ EAX - MSR_
IA32_ MCG_ EBP - MSR_
IA32_ MCG_ EBX - MSR_
IA32_ MCG_ ECX - MSR_
IA32_ MCG_ EDI - MSR_
IA32_ MCG_ EDX - MSR_
IA32_ MCG_ EFLAGS - MSR_
IA32_ MCG_ EIP - MSR_
IA32_ MCG_ ESI - MSR_
IA32_ MCG_ ESP - MSR_
IA32_ MCG_ EXT_ CTL - MSR_
IA32_ MCG_ RESERVED - MSR_
IA32_ MCG_ STATUS - MSR_
IA32_ MCU_ OPT_ CTRL - MSR_
IA32_ MISC_ ENABLE - MSR_
IA32_ MISC_ ENABLE_ ADJ_ PREF_ DISABLE - MSR_
IA32_ MISC_ ENABLE_ ADJ_ PREF_ DISABLE_ BIT - MSR_
IA32_ MISC_ ENABLE_ BTS_ UNAVAIL - MSR_
IA32_ MISC_ ENABLE_ BTS_ UNAVAIL_ BIT - MSR_
IA32_ MISC_ ENABLE_ DCU_ PREF_ DISABLE - MSR_
IA32_ MISC_ ENABLE_ DCU_ PREF_ DISABLE_ BIT - MSR_
IA32_ MISC_ ENABLE_ EMON - MSR_
IA32_ MISC_ ENABLE_ EMON_ BIT - MSR_
IA32_ MISC_ ENABLE_ ENHANCED_ SPEEDSTEP - MSR_
IA32_ MISC_ ENABLE_ ENHANCED_ SPEEDSTEP_ BIT - MSR_
IA32_ MISC_ ENABLE_ FAST_ STRING - MSR_
IA32_ MISC_ ENABLE_ FAST_ STRING_ BIT - MSR_
IA32_ MISC_ ENABLE_ FERR - MSR_
IA32_ MISC_ ENABLE_ FERR_ BIT - MSR_
IA32_ MISC_ ENABLE_ FERR_ MULTIPLEX - MSR_
IA32_ MISC_ ENABLE_ FERR_ MULTIPLEX_ BIT - MSR_
IA32_ MISC_ ENABLE_ IP_ PREF_ DISABLE - MSR_
IA32_ MISC_ ENABLE_ IP_ PREF_ DISABLE_ BIT - MSR_
IA32_ MISC_ ENABLE_ L1D_ CONTEXT - MSR_
IA32_ MISC_ ENABLE_ L1D_ CONTEXT_ BIT - MSR_
IA32_ MISC_ ENABLE_ L3CACHE_ DISABLE - MSR_
IA32_ MISC_ ENABLE_ L3CACHE_ DISABLE_ BIT - MSR_
IA32_ MISC_ ENABLE_ LIMIT_ CPUID - MSR_
IA32_ MISC_ ENABLE_ LIMIT_ CPUID_ BIT - MSR_
IA32_ MISC_ ENABLE_ MWAIT - MSR_
IA32_ MISC_ ENABLE_ MWAIT_ BIT - MSR_
IA32_ MISC_ ENABLE_ PEBS_ UNAVAIL - MSR_
IA32_ MISC_ ENABLE_ PEBS_ UNAVAIL_ BIT - MSR_
IA32_ MISC_ ENABLE_ PREFETCH_ DISABLE - MSR_
IA32_ MISC_ ENABLE_ PREFETCH_ DISABLE_ BIT - MSR_
IA32_ MISC_ ENABLE_ SPEEDSTEP_ LOCK - MSR_
IA32_ MISC_ ENABLE_ SPEEDSTEP_ LOCK_ BIT - MSR_
IA32_ MISC_ ENABLE_ SPLIT_ LOCK_ DISABLE - MSR_
IA32_ MISC_ ENABLE_ SPLIT_ LOCK_ DISABLE_ BIT - MSR_
IA32_ MISC_ ENABLE_ SUPPRESS_ LOCK - MSR_
IA32_ MISC_ ENABLE_ SUPPRESS_ LOCK_ BIT - MSR_
IA32_ MISC_ ENABLE_ TCC - MSR_
IA32_ MISC_ ENABLE_ TCC_ BIT - MSR_
IA32_ MISC_ ENABLE_ TM1 - MSR_
IA32_ MISC_ ENABLE_ TM2 - MSR_
IA32_ MISC_ ENABLE_ TM1_ BIT - MSR_
IA32_ MISC_ ENABLE_ TM2_ BIT - MSR_
IA32_ MISC_ ENABLE_ TURBO_ DISABLE - MSR_
IA32_ MISC_ ENABLE_ TURBO_ DISABLE_ BIT - MSR_
IA32_ MISC_ ENABLE_ X87_ COMPAT - MSR_
IA32_ MISC_ ENABLE_ X87_ COMPAT_ BIT - MSR_
IA32_ MISC_ ENABLE_ XD_ DISABLE - MSR_
IA32_ MISC_ ENABLE_ XD_ DISABLE_ BIT - MSR_
IA32_ MISC_ ENABLE_ XTPR_ DISABLE - MSR_
IA32_ MISC_ ENABLE_ XTPR_ DISABLE_ BIT - MSR_
IA32_ MKTME_ KEYID_ PARTITIONING - MSR_
IA32_ MPERF - MSR_
IA32_ P5_ MC_ ADDR - MSR_
IA32_ P5_ MC_ TYPE - MSR_
IA32_ PACKAGE_ THERM_ INTERRUPT - MSR_
IA32_ PACKAGE_ THERM_ STATUS - MSR_
IA32_ PASID - MSR_
IA32_ PEBS_ ENABLE - MSR_
IA32_ PERFCT R0 - MSR_
IA32_ PERFCT R1 - MSR_
IA32_ PERF_ CAPABILITIES - MSR_
IA32_ PERF_ CTL - MSR_
IA32_ PERF_ STATUS - MSR_
IA32_ PL0_ SSP - MSR_
IA32_ PL1_ SSP - MSR_
IA32_ PL2_ SSP - MSR_
IA32_ PL3_ SSP - MSR_
IA32_ PLATFORM_ ID - MSR_
IA32_ PMC0 - MSR_
IA32_ PMC_ V6_ FX0_ CTR - MSR_
IA32_ PMC_ V6_ GP0_ CFG_ A - MSR_
IA32_ PMC_ V6_ GP0_ CTR - MSR_
IA32_ PMC_ V6_ STEP - MSR_
IA32_ POWER_ CTL - MSR_
IA32_ POWER_ CTL_ BIT_ EE - MSR_
IA32_ PQR_ ASSOC - MSR_
IA32_ PRED_ CMD - MSR_
IA32_ QM_ CTR - MSR_
IA32_ QM_ EVTSEL - MSR_
IA32_ RTIT_ ADDR0_ A - MSR_
IA32_ RTIT_ ADDR0_ B - MSR_
IA32_ RTIT_ ADDR1_ A - MSR_
IA32_ RTIT_ ADDR1_ B - MSR_
IA32_ RTIT_ ADDR2_ A - MSR_
IA32_ RTIT_ ADDR2_ B - MSR_
IA32_ RTIT_ ADDR3_ A - MSR_
IA32_ RTIT_ ADDR3_ B - MSR_
IA32_ RTIT_ CR3_ MATCH - MSR_
IA32_ RTIT_ CTL - MSR_
IA32_ RTIT_ OUTPUT_ BASE - MSR_
IA32_ RTIT_ OUTPUT_ MASK - MSR_
IA32_ RTIT_ STATUS - MSR_
IA32_ SGXLEPUBKEYHAS H0 - MSR_
IA32_ SGXLEPUBKEYHAS H1 - MSR_
IA32_ SGXLEPUBKEYHAS H2 - MSR_
IA32_ SGXLEPUBKEYHAS H3 - MSR_
IA32_ SMBASE - MSR_
IA32_ SMBA_ BW_ BASE - MSR_
IA32_ SMM_ MONITOR_ CTL - MSR_
IA32_ SPEC_ CTRL - MSR_
IA32_ SYSENTER_ CS - MSR_
IA32_ SYSENTER_ EIP - MSR_
IA32_ SYSENTER_ ESP - MSR_
IA32_ S_ CET - MSR_
IA32_ TEMPERATURE_ TARGET - MSR_
IA32_ THERM_ CONTROL - MSR_
IA32_ THERM_ INTERRUPT - MSR_
IA32_ THERM_ STATUS - MSR_
IA32_ TSC - MSR_
IA32_ TSC_ ADJUST - MSR_
IA32_ TSC_ DEADLINE - MSR_
IA32_ TSX_ CTRL - MSR_
IA32_ UCODE_ REV - MSR_
IA32_ UCODE_ WRITE - MSR_
IA32_ UMWAIT_ CONTROL - MSR_
IA32_ UMWAIT_ CONTROL_ TIME_ MASK - MSR_
IA32_ U_ CET - MSR_
IA32_ VMX_ BASIC - MSR_
IA32_ VMX_ CR0_ FIXE D0 - MSR_
IA32_ VMX_ CR0_ FIXE D1 - MSR_
IA32_ VMX_ CR4_ FIXE D0 - MSR_
IA32_ VMX_ CR4_ FIXE D1 - MSR_
IA32_ VMX_ ENTRY_ CTLS - MSR_
IA32_ VMX_ EPT_ VPID_ CAP - MSR_
IA32_ VMX_ EXIT_ CTLS - MSR_
IA32_ VMX_ MISC - MSR_
IA32_ VMX_ PINBASED_ CTLS - MSR_
IA32_ VMX_ PROCBASED_ CTLS - MSR_
IA32_ VMX_ PROCBASED_ CTLS2 - MSR_
IA32_ VMX_ PROCBASED_ CTLS3 - MSR_
IA32_ VMX_ TRUE_ ENTRY_ CTLS - MSR_
IA32_ VMX_ TRUE_ EXIT_ CTLS - MSR_
IA32_ VMX_ TRUE_ PINBASED_ CTLS - MSR_
IA32_ VMX_ TRUE_ PROCBASED_ CTLS - MSR_
IA32_ VMX_ VMCS_ ENUM - MSR_
IA32_ VMX_ VMFUNC - MSR_
IA32_ XAPIC_ DISABLE_ STATUS - MSR_
IA32_ XFD - MSR_
IA32_ XFD_ ERR - MSR_
IA32_ XSS - MSR_
IDT_ FCR1 - MSR_
IDT_ FCR2 - MSR_
IDT_ FCR3 - MSR_
IDT_ FCR4 - MSR_
IDT_ MCR0 - MSR_
IDT_ MCR1 - MSR_
IDT_ MCR2 - MSR_
IDT_ MCR3 - MSR_
IDT_ MCR4 - MSR_
IDT_ MCR5 - MSR_
IDT_ MCR6 - MSR_
IDT_ MCR7 - MSR_
IDT_ MCR_ CTRL - MSR_
INTEGRITY_ CAPS - MSR_
INTEGRITY_ CAPS_ ARRAY_ BIST_ BIT - MSR_
INTEGRITY_ CAPS_ PERIODIC_ BIST_ BIT - MSR_
INTEGRITY_ CAPS_ SBAF_ BIT - MSR_
K6_ EPMR - MSR_
K6_ PFIR - MSR_
K6_ PSOR - MSR_
K6_ UWCCR - MSR_
K6_ WHCR - MSR_
K7_ CLK_ CTL - MSR_
K7_ EVNTSE L0 - MSR_
K7_ EVNTSE L1 - MSR_
K7_ EVNTSE L2 - MSR_
K7_ EVNTSE L3 - MSR_
K7_ FID_ VID_ CTL - MSR_
K7_ FID_ VID_ STATUS - MSR_
K7_ HWCR - MSR_
K7_ HWCR_ CPB_ DIS_ BIT - MSR_
K7_ HWCR_ IRPERF_ EN_ BIT - MSR_
K7_ HWCR_ SMMLOCK_ BIT - MSR_
K7_ PERFCT R0 - MSR_
K7_ PERFCT R1 - MSR_
K7_ PERFCT R2 - MSR_
K7_ PERFCT R3 - MSR_
K8_ INT_ PENDING_ MSG - MSR_
K8_ TOP_ MEM1 - MSR_
K8_ TOP_ MEM2 - MSR_
K8_ TSEG_ ADDR - MSR_
K8_ TSEG_ MASK - MSR_
KERNEL_ GS_ BASE - MSR_
KNC_ EVNTSE L0 - MSR_
KNC_ EVNTSE L1 - MSR_
KNC_ PERFCT R0 - MSR_
KNC_ PERFCT R1 - MSR_
KNL_ CORE_ C6_ RESIDENCY - MSR_
LBR_ CORE_ FROM - MSR_
LBR_ CORE_ TO - MSR_
LBR_ INFO_ 0 - MSR_
LBR_ NHM_ FROM - MSR_
LBR_ NHM_ TO - MSR_
LBR_ SELECT - MSR_
LBR_ TOS - MSR_
LSTAR - MSR_
MC6_ DEMOTION_ POLICY_ CONFIG - MSR_
MISC_ FEATURES_ ENABLES - MSR_
MISC_ FEATURES_ ENABLES_ CPUID_ FAULT_ BIT - MSR_
MISC_ FEATURES_ ENABLES_ RING3MWAIT_ BIT - MSR_
MISC_ FEATURE_ CONTROL - MSR_
MISC_ PWR_ MGMT - MSR_
MODULE_ C6_ RES_ MS - MSR_
MTRRcap - MSR_
MTRRdef Type - MSR_
MTRRfix4K_ C0000 - MSR_
MTRRfix4K_ C8000 - MSR_
MTRRfix4K_ D0000 - MSR_
MTRRfix4K_ D8000 - MSR_
MTRRfix4K_ E0000 - MSR_
MTRRfix4K_ E8000 - MSR_
MTRRfix4K_ F0000 - MSR_
MTRRfix4K_ F8000 - MSR_
MTRRfix16K_ 80000 - MSR_
MTRRfix16K_ A0000 - MSR_
MTRRfix64K_ 00000 - MSR_
OFFCORE_ RSP_ 0 - MSR_
OFFCORE_ RSP_ 1 - MSR_
P4_ ALF_ ESCR0 - MSR_
P4_ ALF_ ESCR1 - MSR_
P4_ BPU_ CCCR0 - MSR_
P4_ BPU_ CCCR1 - MSR_
P4_ BPU_ CCCR2 - MSR_
P4_ BPU_ CCCR3 - MSR_
P4_ BPU_ ESCR0 - MSR_
P4_ BPU_ ESCR1 - MSR_
P4_ BPU_ PERFCT R0 - MSR_
P4_ BPU_ PERFCT R1 - MSR_
P4_ BPU_ PERFCT R2 - MSR_
P4_ BPU_ PERFCT R3 - MSR_
P4_ BSU_ ESCR0 - MSR_
P4_ BSU_ ESCR1 - MSR_
P4_ CRU_ ESCR0 - MSR_
P4_ CRU_ ESCR1 - MSR_
P4_ CRU_ ESCR2 - MSR_
P4_ CRU_ ESCR3 - MSR_
P4_ CRU_ ESCR4 - MSR_
P4_ CRU_ ESCR5 - MSR_
P4_ DAC_ ESCR0 - MSR_
P4_ DAC_ ESCR1 - MSR_
P4_ FIRM_ ESCR0 - MSR_
P4_ FIRM_ ESCR1 - MSR_
P4_ FLAME_ CCCR0 - MSR_
P4_ FLAME_ CCCR1 - MSR_
P4_ FLAME_ CCCR2 - MSR_
P4_ FLAME_ CCCR3 - MSR_
P4_ FLAME_ ESCR0 - MSR_
P4_ FLAME_ ESCR1 - MSR_
P4_ FLAME_ PERFCT R0 - MSR_
P4_ FLAME_ PERFCT R1 - MSR_
P4_ FLAME_ PERFCT R2 - MSR_
P4_ FLAME_ PERFCT R3 - MSR_
P4_ FSB_ ESCR0 - MSR_
P4_ FSB_ ESCR1 - MSR_
P4_ IQ_ CCCR0 - MSR_
P4_ IQ_ CCCR1 - MSR_
P4_ IQ_ CCCR2 - MSR_
P4_ IQ_ CCCR3 - MSR_
P4_ IQ_ CCCR4 - MSR_
P4_ IQ_ CCCR5 - MSR_
P4_ IQ_ ESCR0 - MSR_
P4_ IQ_ ESCR1 - MSR_
P4_ IQ_ PERFCT R0 - MSR_
P4_ IQ_ PERFCT R1 - MSR_
P4_ IQ_ PERFCT R2 - MSR_
P4_ IQ_ PERFCT R3 - MSR_
P4_ IQ_ PERFCT R4 - MSR_
P4_ IQ_ PERFCT R5 - MSR_
P4_ IS_ ESCR0 - MSR_
P4_ IS_ ESCR1 - MSR_
P4_ ITLB_ ESCR0 - MSR_
P4_ ITLB_ ESCR1 - MSR_
P4_ IX_ ESCR0 - MSR_
P4_ IX_ ESCR1 - MSR_
P4_ MOB_ ESCR0 - MSR_
P4_ MOB_ ESCR1 - MSR_
P4_ MS_ CCCR0 - MSR_
P4_ MS_ CCCR1 - MSR_
P4_ MS_ CCCR2 - MSR_
P4_ MS_ CCCR3 - MSR_
P4_ MS_ ESCR0 - MSR_
P4_ MS_ ESCR1 - MSR_
P4_ MS_ PERFCT R0 - MSR_
P4_ MS_ PERFCT R1 - MSR_
P4_ MS_ PERFCT R2 - MSR_
P4_ MS_ PERFCT R3 - MSR_
P4_ PEBS_ MATRIX_ VERT - MSR_
P4_ PMH_ ESCR0 - MSR_
P4_ PMH_ ESCR1 - MSR_
P4_ RAT_ ESCR0 - MSR_
P4_ RAT_ ESCR1 - MSR_
P4_ SAAT_ ESCR0 - MSR_
P4_ SAAT_ ESCR1 - MSR_
P4_ SSU_ ESCR0 - MSR_
P4_ SSU_ ESCR1 - MSR_
P4_ TBPU_ ESCR0 - MSR_
P4_ TBPU_ ESCR1 - MSR_
P4_ TC_ ESCR0 - MSR_
P4_ TC_ ESCR1 - MSR_
P4_ U2L_ ESCR0 - MSR_
P4_ U2L_ ESCR1 - MSR_
P6_ EVNTSE L0 - MSR_
P6_ EVNTSE L1 - MSR_
P6_ PERFCT R0 - MSR_
P6_ PERFCT R1 - MSR_
PEBS_ DATA_ CFG - MSR_
PEBS_ FRONTEND - MSR_
PEBS_ LD_ LAT_ THRESHOLD - MSR_
PERF_ LIMIT_ REASONS - MSR_
PERF_ METRICS - MSR_
PKGC3_ IRTL - MSR_
PKGC6_ IRTL - MSR_
PKGC7_ IRTL - MSR_
PKGC8_ IRTL - MSR_
PKGC9_ IRTL - MSR_
PKGC10_ IRTL - MSR_
PKG_ ANY_ CORE_ C0_ RES - MSR_
PKG_ ANY_ GFXE_ C0_ RES - MSR_
PKG_ BOTH_ CORE_ GFXE_ C0_ RES - MSR_
PKG_ C2_ RESIDENCY - MSR_
PKG_ C3_ RESIDENCY - MSR_
PKG_ C6_ RESIDENCY - MSR_
PKG_ C7_ RESIDENCY - MSR_
PKG_ C8_ RESIDENCY - MSR_
PKG_ C9_ RESIDENCY - MSR_
PKG_ C10_ RESIDENCY - MSR_
PKG_ CST_ CONFIG_ CONTROL - MSR_
PKG_ ENERGY_ STATUS - MSR_
PKG_ PERF_ STATUS - MSR_
PKG_ POWER_ INFO - MSR_
PKG_ POWER_ LIMIT - MSR_
PKG_ WEIGHTED_ CORE_ C0_ RES - MSR_
PLATFORM_ ENERGY_ STATUS - MSR_
PLATFORM_ INFO - MSR_
PLATFORM_ INFO_ CPUID_ FAULT_ BIT - MSR_
PM_ ENABLE - MSR_
PP0_ ENERGY_ STATUS - MSR_
PP0_ PERF_ STATUS - MSR_
PP0_ POLICY - MSR_
PP0_ POWER_ LIMIT - MSR_
PP1_ ENERGY_ STATUS - MSR_
PP1_ POLICY - MSR_
PP1_ POWER_ LIMIT - MSR_
PPERF - MSR_
PPIN - MSR_
PPIN_ CTL - MSR_
RAPL_ POWER_ UNIT - MSR_
RELOAD_ FIXED_ CTR0 - MSR_
RELOAD_ PMC0 - MSR_
RING_ PERF_ LIMIT_ REASONS - MSR_
RMID_ SNC_ CONFIG - MSR_
SECONDARY_ TURBO_ RATIO_ LIMIT - MSR_
SMI_ COUNT - MSR_
SNOOP_ RSP_ 0 - MSR_
SNOOP_ RSP_ 1 - MSR_
STAR - MSR_
SVSM_ CAA - MSR_
SYSCALL_ MASK - MSR_
TEST_ CTRL - MSR_
TEST_ CTRL_ SPLIT_ LOCK_ DETECT_ BIT - MSR_
TFA_ RTM_ FORCE_ ABORT_ BIT - MSR_
TFA_ SDV_ ENABLE_ RTM_ BIT - MSR_
TFA_ TSX_ CPUID_ CLEAR_ BIT - MSR_
THER M2_ CTL - MSR_
THER M2_ CTL_ TM_ SELECT - MSR_
TMTA_ LONGRUN_ CTRL - MSR_
TMTA_ LONGRUN_ FLAGS - MSR_
TMTA_ LRTI_ READOUT - MSR_
TMTA_ LRTI_ VOLT_ MHZ - MSR_
TSC_ AUX - MSR_
TSX_ FORCE_ ABORT - MSR_
TURBO_ ACTIVATION_ RATIO - MSR_
TURBO_ RATIO_ LIMIT - MSR_
TURBO_ RATIO_ LIMI T1 - MSR_
TURBO_ RATIO_ LIMI T2 - MSR_
VIA_ BCR2 - MSR_
VIA_ FCR - MSR_
VIA_ LONGHAUL - MSR_
VIA_ RNG - MSR_
VM_ CR - MSR_
VM_ HSAVE_ PA - MSR_
VM_ IGNNE - MSR_
VR_ CURRENT_ CONFIG - MSR_
ZEN2_ SPECTRAL_ CHICKEN - MSR_
ZEN4_ BP_ CFG - MSR_
ZEN4_ BP_ CFG_ SHARED_ BTB_ FIX_ BIT