vmm/arch/x86_64/generated/
msr_index.rs1#![allow(
7 non_camel_case_types,
8 non_upper_case_globals,
9 dead_code,
10 non_snake_case,
11 clippy::ptr_as_ptr,
12 clippy::undocumented_unsafe_blocks,
13 missing_debug_implementations,
14 clippy::tests_outside_test_module,
15 unsafe_op_in_unsafe_fn,
16 clippy::redundant_static_lifetimes
17)]
18
19pub const MSR_EFER: u32 = 0xc0000080;
20pub const MSR_STAR: u32 = 0xc0000081;
21pub const MSR_LSTAR: u32 = 0xc0000082;
22pub const MSR_CSTAR: u32 = 0xc0000083;
23pub const MSR_SYSCALL_MASK: u32 = 0xc0000084;
24pub const MSR_FS_BASE: u32 = 0xc0000100;
25pub const MSR_GS_BASE: u32 = 0xc0000101;
26pub const MSR_KERNEL_GS_BASE: u32 = 0xc0000102;
27pub const MSR_TSC_AUX: u32 = 0xc0000103;
28pub const MSR_IA32_FRED_RSP0: u32 = 0x1cc;
29pub const MSR_IA32_FRED_RSP1: u32 = 0x1cd;
30pub const MSR_IA32_FRED_RSP2: u32 = 0x1ce;
31pub const MSR_IA32_FRED_RSP3: u32 = 0x1cf;
32pub const MSR_IA32_FRED_STKLVLS: u32 = 0x1d0;
33pub const MSR_IA32_FRED_SSP1: u32 = 0x1d1;
34pub const MSR_IA32_FRED_SSP2: u32 = 0x1d2;
35pub const MSR_IA32_FRED_SSP3: u32 = 0x1d3;
36pub const MSR_IA32_FRED_CONFIG: u32 = 0x1d4;
37pub const MSR_TEST_CTRL: u32 = 0x33;
38pub const MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT: u32 = 0x1d;
39pub const MSR_IA32_SPEC_CTRL: u32 = 0x48;
40pub const MSR_IA32_PRED_CMD: u32 = 0x49;
41pub const MSR_PPIN_CTL: u32 = 0x4e;
42pub const MSR_PPIN: u32 = 0x4f;
43pub const MSR_IA32_PERFCTR0: u32 = 0xc1;
44pub const MSR_IA32_PERFCTR1: u32 = 0xc2;
45pub const MSR_FSB_FREQ: u32 = 0xcd;
46pub const MSR_PLATFORM_INFO: u32 = 0xce;
47pub const MSR_PLATFORM_INFO_CPUID_FAULT_BIT: u32 = 0x1f;
48pub const MSR_IA32_UMWAIT_CONTROL: u32 = 0xe1;
49pub const MSR_IA32_UMWAIT_CONTROL_TIME_MASK: i32 = -4;
50pub const MSR_IA32_CORE_CAPS: u32 = 0xcf;
51pub const MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT: u32 = 0x2;
52pub const MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT: u32 = 0x5;
53pub const MSR_PKG_CST_CONFIG_CONTROL: u32 = 0xe2;
54pub const MSR_MTRRcap: u32 = 0xfe;
55pub const MSR_IA32_ARCH_CAPABILITIES: u32 = 0x10a;
56pub const MSR_IA32_FLUSH_CMD: u32 = 0x10b;
57pub const MSR_IA32_BBL_CR_CTL: u32 = 0x119;
58pub const MSR_IA32_BBL_CR_CTL3: u32 = 0x11e;
59pub const MSR_IA32_TSX_CTRL: u32 = 0x122;
60pub const MSR_IA32_MCU_OPT_CTRL: u32 = 0x123;
61pub const MSR_IA32_SYSENTER_CS: u32 = 0x174;
62pub const MSR_IA32_SYSENTER_ESP: u32 = 0x175;
63pub const MSR_IA32_SYSENTER_EIP: u32 = 0x176;
64pub const MSR_IA32_MCG_CAP: u32 = 0x179;
65pub const MSR_IA32_MCG_STATUS: u32 = 0x17a;
66pub const MSR_IA32_MCG_CTL: u32 = 0x17b;
67pub const MSR_ERROR_CONTROL: u32 = 0x17f;
68pub const MSR_IA32_MCG_EXT_CTL: u32 = 0x4d0;
69pub const MSR_OFFCORE_RSP_0: u32 = 0x1a6;
70pub const MSR_OFFCORE_RSP_1: u32 = 0x1a7;
71pub const MSR_TURBO_RATIO_LIMIT: u32 = 0x1ad;
72pub const MSR_TURBO_RATIO_LIMIT1: u32 = 0x1ae;
73pub const MSR_TURBO_RATIO_LIMIT2: u32 = 0x1af;
74pub const MSR_SNOOP_RSP_0: u32 = 0x1328;
75pub const MSR_SNOOP_RSP_1: u32 = 0x1329;
76pub const MSR_LBR_SELECT: u32 = 0x1c8;
77pub const MSR_LBR_TOS: u32 = 0x1c9;
78pub const MSR_IA32_POWER_CTL: u32 = 0x1fc;
79pub const MSR_IA32_POWER_CTL_BIT_EE: u32 = 0x13;
80pub const MSR_INTEGRITY_CAPS: u32 = 0x2d9;
81pub const MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT: u32 = 0x2;
82pub const MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT: u32 = 0x4;
83pub const MSR_INTEGRITY_CAPS_SBAF_BIT: u32 = 0x8;
84pub const MSR_LBR_NHM_FROM: u32 = 0x680;
85pub const MSR_LBR_NHM_TO: u32 = 0x6c0;
86pub const MSR_LBR_CORE_FROM: u32 = 0x40;
87pub const MSR_LBR_CORE_TO: u32 = 0x60;
88pub const MSR_LBR_INFO_0: u32 = 0xdc0;
89pub const MSR_ARCH_LBR_CTL: u32 = 0x14ce;
90pub const MSR_ARCH_LBR_DEPTH: u32 = 0x14cf;
91pub const MSR_ARCH_LBR_FROM_0: u32 = 0x1500;
92pub const MSR_ARCH_LBR_TO_0: u32 = 0x1600;
93pub const MSR_ARCH_LBR_INFO_0: u32 = 0x1200;
94pub const MSR_IA32_PEBS_ENABLE: u32 = 0x3f1;
95pub const MSR_PEBS_DATA_CFG: u32 = 0x3f2;
96pub const MSR_IA32_DS_AREA: u32 = 0x600;
97pub const MSR_IA32_PERF_CAPABILITIES: u32 = 0x345;
98pub const MSR_PEBS_LD_LAT_THRESHOLD: u32 = 0x3f6;
99pub const MSR_IA32_RTIT_CTL: u32 = 0x570;
100pub const MSR_IA32_RTIT_STATUS: u32 = 0x571;
101pub const MSR_IA32_RTIT_ADDR0_A: u32 = 0x580;
102pub const MSR_IA32_RTIT_ADDR0_B: u32 = 0x581;
103pub const MSR_IA32_RTIT_ADDR1_A: u32 = 0x582;
104pub const MSR_IA32_RTIT_ADDR1_B: u32 = 0x583;
105pub const MSR_IA32_RTIT_ADDR2_A: u32 = 0x584;
106pub const MSR_IA32_RTIT_ADDR2_B: u32 = 0x585;
107pub const MSR_IA32_RTIT_ADDR3_A: u32 = 0x586;
108pub const MSR_IA32_RTIT_ADDR3_B: u32 = 0x587;
109pub const MSR_IA32_RTIT_CR3_MATCH: u32 = 0x572;
110pub const MSR_IA32_RTIT_OUTPUT_BASE: u32 = 0x560;
111pub const MSR_IA32_RTIT_OUTPUT_MASK: u32 = 0x561;
112pub const MSR_MTRRfix64K_00000: u32 = 0x250;
113pub const MSR_MTRRfix16K_80000: u32 = 0x258;
114pub const MSR_MTRRfix16K_A0000: u32 = 0x259;
115pub const MSR_MTRRfix4K_C0000: u32 = 0x268;
116pub const MSR_MTRRfix4K_C8000: u32 = 0x269;
117pub const MSR_MTRRfix4K_D0000: u32 = 0x26a;
118pub const MSR_MTRRfix4K_D8000: u32 = 0x26b;
119pub const MSR_MTRRfix4K_E0000: u32 = 0x26c;
120pub const MSR_MTRRfix4K_E8000: u32 = 0x26d;
121pub const MSR_MTRRfix4K_F0000: u32 = 0x26e;
122pub const MSR_MTRRfix4K_F8000: u32 = 0x26f;
123pub const MSR_MTRRdefType: u32 = 0x2ff;
124pub const MSR_IA32_CR_PAT: u32 = 0x277;
125pub const MSR_IA32_DEBUGCTLMSR: u32 = 0x1d9;
126pub const MSR_IA32_LASTBRANCHFROMIP: u32 = 0x1db;
127pub const MSR_IA32_LASTBRANCHTOIP: u32 = 0x1dc;
128pub const MSR_IA32_LASTINTFROMIP: u32 = 0x1dd;
129pub const MSR_IA32_LASTINTTOIP: u32 = 0x1de;
130pub const MSR_IA32_PASID: u32 = 0xd93;
131pub const MSR_PEBS_FRONTEND: u32 = 0x3f7;
132pub const MSR_IA32_MC0_CTL: u32 = 0x400;
133pub const MSR_IA32_MC0_STATUS: u32 = 0x401;
134pub const MSR_IA32_MC0_ADDR: u32 = 0x402;
135pub const MSR_IA32_MC0_MISC: u32 = 0x403;
136pub const MSR_PKG_C3_RESIDENCY: u32 = 0x3f8;
137pub const MSR_PKG_C6_RESIDENCY: u32 = 0x3f9;
138pub const MSR_ATOM_PKG_C6_RESIDENCY: u32 = 0x3fa;
139pub const MSR_PKG_C7_RESIDENCY: u32 = 0x3fa;
140pub const MSR_CORE_C3_RESIDENCY: u32 = 0x3fc;
141pub const MSR_CORE_C6_RESIDENCY: u32 = 0x3fd;
142pub const MSR_CORE_C7_RESIDENCY: u32 = 0x3fe;
143pub const MSR_KNL_CORE_C6_RESIDENCY: u32 = 0x3ff;
144pub const MSR_PKG_C2_RESIDENCY: u32 = 0x60d;
145pub const MSR_PKG_C8_RESIDENCY: u32 = 0x630;
146pub const MSR_PKG_C9_RESIDENCY: u32 = 0x631;
147pub const MSR_PKG_C10_RESIDENCY: u32 = 0x632;
148pub const MSR_PKGC3_IRTL: u32 = 0x60a;
149pub const MSR_PKGC6_IRTL: u32 = 0x60b;
150pub const MSR_PKGC7_IRTL: u32 = 0x60c;
151pub const MSR_PKGC8_IRTL: u32 = 0x633;
152pub const MSR_PKGC9_IRTL: u32 = 0x634;
153pub const MSR_PKGC10_IRTL: u32 = 0x635;
154pub const MSR_VR_CURRENT_CONFIG: u32 = 0x601;
155pub const MSR_RAPL_POWER_UNIT: u32 = 0x606;
156pub const MSR_PKG_POWER_LIMIT: u32 = 0x610;
157pub const MSR_PKG_ENERGY_STATUS: u32 = 0x611;
158pub const MSR_PKG_PERF_STATUS: u32 = 0x613;
159pub const MSR_PKG_POWER_INFO: u32 = 0x614;
160pub const MSR_DRAM_POWER_LIMIT: u32 = 0x618;
161pub const MSR_DRAM_ENERGY_STATUS: u32 = 0x619;
162pub const MSR_DRAM_PERF_STATUS: u32 = 0x61b;
163pub const MSR_DRAM_POWER_INFO: u32 = 0x61c;
164pub const MSR_PP0_POWER_LIMIT: u32 = 0x638;
165pub const MSR_PP0_ENERGY_STATUS: u32 = 0x639;
166pub const MSR_PP0_POLICY: u32 = 0x63a;
167pub const MSR_PP0_PERF_STATUS: u32 = 0x63b;
168pub const MSR_PP1_POWER_LIMIT: u32 = 0x640;
169pub const MSR_PP1_ENERGY_STATUS: u32 = 0x641;
170pub const MSR_PP1_POLICY: u32 = 0x642;
171pub const MSR_AMD_RAPL_POWER_UNIT: u32 = 0xc0010299;
172pub const MSR_AMD_CORE_ENERGY_STATUS: u32 = 0xc001029a;
173pub const MSR_AMD_PKG_ENERGY_STATUS: u32 = 0xc001029b;
174pub const MSR_CONFIG_TDP_NOMINAL: u32 = 0x648;
175pub const MSR_CONFIG_TDP_LEVEL_1: u32 = 0x649;
176pub const MSR_CONFIG_TDP_LEVEL_2: u32 = 0x64a;
177pub const MSR_CONFIG_TDP_CONTROL: u32 = 0x64b;
178pub const MSR_TURBO_ACTIVATION_RATIO: u32 = 0x64c;
179pub const MSR_PLATFORM_ENERGY_STATUS: u32 = 0x64d;
180pub const MSR_SECONDARY_TURBO_RATIO_LIMIT: u32 = 0x650;
181pub const MSR_PKG_WEIGHTED_CORE_C0_RES: u32 = 0x658;
182pub const MSR_PKG_ANY_CORE_C0_RES: u32 = 0x659;
183pub const MSR_PKG_ANY_GFXE_C0_RES: u32 = 0x65a;
184pub const MSR_PKG_BOTH_CORE_GFXE_C0_RES: u32 = 0x65b;
185pub const MSR_CORE_C1_RES: u32 = 0x660;
186pub const MSR_MODULE_C6_RES_MS: u32 = 0x664;
187pub const MSR_CC6_DEMOTION_POLICY_CONFIG: u32 = 0x668;
188pub const MSR_MC6_DEMOTION_POLICY_CONFIG: u32 = 0x669;
189pub const MSR_ATOM_CORE_RATIOS: u32 = 0x66a;
190pub const MSR_ATOM_CORE_VIDS: u32 = 0x66b;
191pub const MSR_ATOM_CORE_TURBO_RATIOS: u32 = 0x66c;
192pub const MSR_ATOM_CORE_TURBO_VIDS: u32 = 0x66d;
193pub const MSR_CORE_PERF_LIMIT_REASONS: u32 = 0x690;
194pub const MSR_GFX_PERF_LIMIT_REASONS: u32 = 0x6b0;
195pub const MSR_RING_PERF_LIMIT_REASONS: u32 = 0x6b1;
196pub const MSR_IA32_U_CET: u32 = 0x6a0;
197pub const MSR_IA32_S_CET: u32 = 0x6a2;
198pub const MSR_IA32_PL0_SSP: u32 = 0x6a4;
199pub const MSR_IA32_PL1_SSP: u32 = 0x6a5;
200pub const MSR_IA32_PL2_SSP: u32 = 0x6a6;
201pub const MSR_IA32_PL3_SSP: u32 = 0x6a7;
202pub const MSR_IA32_INT_SSP_TAB: u32 = 0x6a8;
203pub const MSR_PPERF: u32 = 0x64e;
204pub const MSR_PERF_LIMIT_REASONS: u32 = 0x64f;
205pub const MSR_PM_ENABLE: u32 = 0x770;
206pub const MSR_HWP_CAPABILITIES: u32 = 0x771;
207pub const MSR_HWP_REQUEST_PKG: u32 = 0x772;
208pub const MSR_HWP_INTERRUPT: u32 = 0x773;
209pub const MSR_HWP_REQUEST: u32 = 0x774;
210pub const MSR_HWP_STATUS: u32 = 0x777;
211pub const MSR_AMD64_MC0_MASK: u32 = 0xc0010044;
212pub const MSR_IA32_MC0_CTL2: u32 = 0x280;
213pub const MSR_P6_PERFCTR0: u32 = 0xc1;
214pub const MSR_P6_PERFCTR1: u32 = 0xc2;
215pub const MSR_P6_EVNTSEL0: u32 = 0x186;
216pub const MSR_P6_EVNTSEL1: u32 = 0x187;
217pub const MSR_KNC_PERFCTR0: u32 = 0x20;
218pub const MSR_KNC_PERFCTR1: u32 = 0x21;
219pub const MSR_KNC_EVNTSEL0: u32 = 0x28;
220pub const MSR_KNC_EVNTSEL1: u32 = 0x29;
221pub const MSR_IA32_PMC0: u32 = 0x4c1;
222pub const MSR_RELOAD_PMC0: u32 = 0x14c1;
223pub const MSR_RELOAD_FIXED_CTR0: u32 = 0x1309;
224pub const MSR_IA32_PMC_V6_GP0_CTR: u32 = 0x1900;
225pub const MSR_IA32_PMC_V6_GP0_CFG_A: u32 = 0x1901;
226pub const MSR_IA32_PMC_V6_FX0_CTR: u32 = 0x1980;
227pub const MSR_IA32_PMC_V6_STEP: u32 = 0x4;
228pub const MSR_IA32_MKTME_KEYID_PARTITIONING: u32 = 0x87;
229pub const MSR_AMD64_PATCH_LEVEL: u32 = 0x8b;
230pub const MSR_AMD64_TSC_RATIO: u32 = 0xc0000104;
231pub const MSR_AMD64_NB_CFG: u32 = 0xc001001f;
232pub const MSR_AMD64_PATCH_LOADER: u32 = 0xc0010020;
233pub const MSR_AMD_PERF_CTL: u32 = 0xc0010062;
234pub const MSR_AMD_PERF_STATUS: u32 = 0xc0010063;
235pub const MSR_AMD_PSTATE_DEF_BASE: u32 = 0xc0010064;
236pub const MSR_AMD64_OSVW_ID_LENGTH: u32 = 0xc0010140;
237pub const MSR_AMD64_OSVW_STATUS: u32 = 0xc0010141;
238pub const MSR_AMD_PPIN_CTL: u32 = 0xc00102f0;
239pub const MSR_AMD_PPIN: u32 = 0xc00102f1;
240pub const MSR_AMD64_CPUID_FN_1: u32 = 0xc0011004;
241pub const MSR_AMD64_LS_CFG: u32 = 0xc0011020;
242pub const MSR_AMD64_DC_CFG: u32 = 0xc0011022;
243pub const MSR_AMD64_TW_CFG: u32 = 0xc0011023;
244pub const MSR_AMD64_DE_CFG: u32 = 0xc0011029;
245pub const MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT: u32 = 0x1;
246pub const MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT: u32 = 0x9;
247pub const MSR_AMD64_BU_CFG2: u32 = 0xc001102a;
248pub const MSR_AMD64_IBSFETCHCTL: u32 = 0xc0011030;
249pub const MSR_AMD64_IBSFETCHLINAD: u32 = 0xc0011031;
250pub const MSR_AMD64_IBSFETCHPHYSAD: u32 = 0xc0011032;
251pub const MSR_AMD64_IBSFETCH_REG_COUNT: u32 = 0x3;
252pub const MSR_AMD64_IBSFETCH_REG_MASK: u32 = 0x7;
253pub const MSR_AMD64_IBSOPCTL: u32 = 0xc0011033;
254pub const MSR_AMD64_IBSOPRIP: u32 = 0xc0011034;
255pub const MSR_AMD64_IBSOPDATA: u32 = 0xc0011035;
256pub const MSR_AMD64_IBSOPDATA2: u32 = 0xc0011036;
257pub const MSR_AMD64_IBSOPDATA3: u32 = 0xc0011037;
258pub const MSR_AMD64_IBSDCLINAD: u32 = 0xc0011038;
259pub const MSR_AMD64_IBSDCPHYSAD: u32 = 0xc0011039;
260pub const MSR_AMD64_IBSOP_REG_COUNT: u32 = 0x7;
261pub const MSR_AMD64_IBSOP_REG_MASK: u32 = 0x7f;
262pub const MSR_AMD64_IBSCTL: u32 = 0xc001103a;
263pub const MSR_AMD64_IBSBRTARGET: u32 = 0xc001103b;
264pub const MSR_AMD64_ICIBSEXTDCTL: u32 = 0xc001103c;
265pub const MSR_AMD64_IBSOPDATA4: u32 = 0xc001103d;
266pub const MSR_AMD64_IBS_REG_COUNT_MAX: u32 = 0x8;
267pub const MSR_AMD64_SVM_AVIC_DOORBELL: u32 = 0xc001011b;
268pub const MSR_AMD64_VM_PAGE_FLUSH: u32 = 0xc001011e;
269pub const MSR_AMD64_SEV_ES_GHCB: u32 = 0xc0010130;
270pub const MSR_AMD64_SEV: u32 = 0xc0010131;
271pub const MSR_AMD64_SEV_ENABLED_BIT: u32 = 0x0;
272pub const MSR_AMD64_SEV_ES_ENABLED_BIT: u32 = 0x1;
273pub const MSR_AMD64_SEV_SNP_ENABLED_BIT: u32 = 0x2;
274pub const MSR_AMD64_SNP_VTOM_BIT: u32 = 0x3;
275pub const MSR_AMD64_SNP_REFLECT_VC_BIT: u32 = 0x4;
276pub const MSR_AMD64_SNP_RESTRICTED_INJ_BIT: u32 = 0x5;
277pub const MSR_AMD64_SNP_ALT_INJ_BIT: u32 = 0x6;
278pub const MSR_AMD64_SNP_DEBUG_SWAP_BIT: u32 = 0x7;
279pub const MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT: u32 = 0x8;
280pub const MSR_AMD64_SNP_BTB_ISOLATION_BIT: u32 = 0x9;
281pub const MSR_AMD64_SNP_VMPL_SSS_BIT: u32 = 0xa;
282pub const MSR_AMD64_SNP_SECURE_TSC_BIT: u32 = 0xb;
283pub const MSR_AMD64_SNP_VMGEXIT_PARAM_BIT: u32 = 0xc;
284pub const MSR_AMD64_SNP_IBS_VIRT_BIT: u32 = 0xe;
285pub const MSR_AMD64_SNP_VMSA_REG_PROT_BIT: u32 = 0x10;
286pub const MSR_AMD64_SNP_SMT_PROT_BIT: u32 = 0x11;
287pub const MSR_AMD64_SNP_RESV_BIT: u32 = 0x12;
288pub const MSR_AMD64_VIRT_SPEC_CTRL: u32 = 0xc001011f;
289pub const MSR_AMD64_RMP_BASE: u32 = 0xc0010132;
290pub const MSR_AMD64_RMP_END: u32 = 0xc0010133;
291pub const MSR_SVSM_CAA: u32 = 0xc001f000;
292pub const MSR_AMD_CPPC_CAP1: u32 = 0xc00102b0;
293pub const MSR_AMD_CPPC_ENABLE: u32 = 0xc00102b1;
294pub const MSR_AMD_CPPC_CAP2: u32 = 0xc00102b2;
295pub const MSR_AMD_CPPC_REQ: u32 = 0xc00102b3;
296pub const MSR_AMD_CPPC_STATUS: u32 = 0xc00102b4;
297pub const MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: u32 = 0xc0000300;
298pub const MSR_AMD64_PERF_CNTR_GLOBAL_CTL: u32 = 0xc0000301;
299pub const MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: u32 = 0xc0000302;
300pub const MSR_AMD64_LBR_SELECT: u32 = 0xc000010e;
301pub const MSR_ZEN4_BP_CFG: u32 = 0xc001102e;
302pub const MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT: u32 = 0x5;
303pub const MSR_F19H_UMC_PERF_CTL: u32 = 0xc0010800;
304pub const MSR_F19H_UMC_PERF_CTR: u32 = 0xc0010801;
305pub const MSR_ZEN2_SPECTRAL_CHICKEN: u32 = 0xc00110e3;
306pub const MSR_F17H_IRPERF: u32 = 0xc00000e9;
307pub const MSR_F16H_L2I_PERF_CTL: u32 = 0xc0010230;
308pub const MSR_F16H_L2I_PERF_CTR: u32 = 0xc0010231;
309pub const MSR_F16H_DR1_ADDR_MASK: u32 = 0xc0011019;
310pub const MSR_F16H_DR2_ADDR_MASK: u32 = 0xc001101a;
311pub const MSR_F16H_DR3_ADDR_MASK: u32 = 0xc001101b;
312pub const MSR_F16H_DR0_ADDR_MASK: u32 = 0xc0011027;
313pub const MSR_F15H_CU_PWR_ACCUMULATOR: u32 = 0xc001007a;
314pub const MSR_F15H_CU_MAX_PWR_ACCUMULATOR: u32 = 0xc001007b;
315pub const MSR_F15H_PERF_CTL: u32 = 0xc0010200;
316pub const MSR_F15H_PERF_CTL0: u32 = 0xc0010200;
317pub const MSR_F15H_PERF_CTL1: u32 = 0xc0010202;
318pub const MSR_F15H_PERF_CTL2: u32 = 0xc0010204;
319pub const MSR_F15H_PERF_CTL3: u32 = 0xc0010206;
320pub const MSR_F15H_PERF_CTL4: u32 = 0xc0010208;
321pub const MSR_F15H_PERF_CTL5: u32 = 0xc001020a;
322pub const MSR_F15H_PERF_CTR: u32 = 0xc0010201;
323pub const MSR_F15H_PERF_CTR0: u32 = 0xc0010201;
324pub const MSR_F15H_PERF_CTR1: u32 = 0xc0010203;
325pub const MSR_F15H_PERF_CTR2: u32 = 0xc0010205;
326pub const MSR_F15H_PERF_CTR3: u32 = 0xc0010207;
327pub const MSR_F15H_PERF_CTR4: u32 = 0xc0010209;
328pub const MSR_F15H_PERF_CTR5: u32 = 0xc001020b;
329pub const MSR_F15H_NB_PERF_CTL: u32 = 0xc0010240;
330pub const MSR_F15H_NB_PERF_CTR: u32 = 0xc0010241;
331pub const MSR_F15H_PTSC: u32 = 0xc0010280;
332pub const MSR_F15H_IC_CFG: u32 = 0xc0011021;
333pub const MSR_F15H_EX_CFG: u32 = 0xc001102c;
334pub const MSR_FAM10H_MMIO_CONF_BASE: u32 = 0xc0010058;
335pub const MSR_FAM10H_NODE_ID: u32 = 0xc001100c;
336pub const MSR_K8_TOP_MEM1: u32 = 0xc001001a;
337pub const MSR_K8_TOP_MEM2: u32 = 0xc001001d;
338pub const MSR_AMD64_SYSCFG: u32 = 0xc0010010;
339pub const MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT: u32 = 0x17;
340pub const MSR_AMD64_SYSCFG_SNP_EN_BIT: u32 = 0x18;
341pub const MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT: u32 = 0x19;
342pub const MSR_AMD64_SYSCFG_MFDM_BIT: u32 = 0x13;
343pub const MSR_K8_INT_PENDING_MSG: u32 = 0xc0010055;
344pub const MSR_K8_TSEG_ADDR: u32 = 0xc0010112;
345pub const MSR_K8_TSEG_MASK: u32 = 0xc0010113;
346pub const MSR_K7_EVNTSEL0: u32 = 0xc0010000;
347pub const MSR_K7_PERFCTR0: u32 = 0xc0010004;
348pub const MSR_K7_EVNTSEL1: u32 = 0xc0010001;
349pub const MSR_K7_PERFCTR1: u32 = 0xc0010005;
350pub const MSR_K7_EVNTSEL2: u32 = 0xc0010002;
351pub const MSR_K7_PERFCTR2: u32 = 0xc0010006;
352pub const MSR_K7_EVNTSEL3: u32 = 0xc0010003;
353pub const MSR_K7_PERFCTR3: u32 = 0xc0010007;
354pub const MSR_K7_CLK_CTL: u32 = 0xc001001b;
355pub const MSR_K7_HWCR: u32 = 0xc0010015;
356pub const MSR_K7_HWCR_SMMLOCK_BIT: u32 = 0x0;
357pub const MSR_K7_HWCR_IRPERF_EN_BIT: u32 = 0x1e;
358pub const MSR_K7_FID_VID_CTL: u32 = 0xc0010041;
359pub const MSR_K7_FID_VID_STATUS: u32 = 0xc0010042;
360pub const MSR_K7_HWCR_CPB_DIS_BIT: u32 = 0x19;
361pub const MSR_K6_WHCR: u32 = 0xc0000082;
362pub const MSR_K6_UWCCR: u32 = 0xc0000085;
363pub const MSR_K6_EPMR: u32 = 0xc0000086;
364pub const MSR_K6_PSOR: u32 = 0xc0000087;
365pub const MSR_K6_PFIR: u32 = 0xc0000088;
366pub const MSR_IDT_FCR1: u32 = 0x107;
367pub const MSR_IDT_FCR2: u32 = 0x108;
368pub const MSR_IDT_FCR3: u32 = 0x109;
369pub const MSR_IDT_FCR4: u32 = 0x10a;
370pub const MSR_IDT_MCR0: u32 = 0x110;
371pub const MSR_IDT_MCR1: u32 = 0x111;
372pub const MSR_IDT_MCR2: u32 = 0x112;
373pub const MSR_IDT_MCR3: u32 = 0x113;
374pub const MSR_IDT_MCR4: u32 = 0x114;
375pub const MSR_IDT_MCR5: u32 = 0x115;
376pub const MSR_IDT_MCR6: u32 = 0x116;
377pub const MSR_IDT_MCR7: u32 = 0x117;
378pub const MSR_IDT_MCR_CTRL: u32 = 0x120;
379pub const MSR_VIA_FCR: u32 = 0x1107;
380pub const MSR_VIA_LONGHAUL: u32 = 0x110a;
381pub const MSR_VIA_RNG: u32 = 0x110b;
382pub const MSR_VIA_BCR2: u32 = 0x1147;
383pub const MSR_TMTA_LONGRUN_CTRL: u32 = 0x80868010;
384pub const MSR_TMTA_LONGRUN_FLAGS: u32 = 0x80868011;
385pub const MSR_TMTA_LRTI_READOUT: u32 = 0x80868018;
386pub const MSR_TMTA_LRTI_VOLT_MHZ: u32 = 0x8086801a;
387pub const MSR_IA32_P5_MC_ADDR: u32 = 0x0;
388pub const MSR_IA32_P5_MC_TYPE: u32 = 0x1;
389pub const MSR_IA32_TSC: u32 = 0x10;
390pub const MSR_IA32_PLATFORM_ID: u32 = 0x17;
391pub const MSR_IA32_EBL_CR_POWERON: u32 = 0x2a;
392pub const MSR_EBC_FREQUENCY_ID: u32 = 0x2c;
393pub const MSR_SMI_COUNT: u32 = 0x34;
394pub const MSR_IA32_FEAT_CTL: u32 = 0x3a;
395pub const MSR_IA32_TSC_ADJUST: u32 = 0x3b;
396pub const MSR_IA32_BNDCFGS: u32 = 0xd90;
397pub const MSR_IA32_BNDCFGS_RSVD: u32 = 0xffc;
398pub const MSR_IA32_XFD: u32 = 0x1c4;
399pub const MSR_IA32_XFD_ERR: u32 = 0x1c5;
400pub const MSR_IA32_XSS: u32 = 0xda0;
401pub const MSR_IA32_APICBASE: u32 = 0x1b;
402pub const MSR_IA32_APICBASE_BSP: u32 = 0x100;
403pub const MSR_IA32_APICBASE_ENABLE: u32 = 0x800;
404pub const MSR_IA32_APICBASE_BASE: u32 = 0xfffff000;
405pub const MSR_IA32_UCODE_WRITE: u32 = 0x79;
406pub const MSR_IA32_UCODE_REV: u32 = 0x8b;
407pub const MSR_IA32_SGXLEPUBKEYHASH0: u32 = 0x8c;
408pub const MSR_IA32_SGXLEPUBKEYHASH1: u32 = 0x8d;
409pub const MSR_IA32_SGXLEPUBKEYHASH2: u32 = 0x8e;
410pub const MSR_IA32_SGXLEPUBKEYHASH3: u32 = 0x8f;
411pub const MSR_IA32_SMM_MONITOR_CTL: u32 = 0x9b;
412pub const MSR_IA32_SMBASE: u32 = 0x9e;
413pub const MSR_IA32_PERF_STATUS: u32 = 0x198;
414pub const MSR_IA32_PERF_CTL: u32 = 0x199;
415pub const MSR_AMD_DBG_EXTN_CFG: u32 = 0xc000010f;
416pub const MSR_AMD_SAMP_BR_FROM: u32 = 0xc0010300;
417pub const MSR_IA32_MPERF: u32 = 0xe7;
418pub const MSR_IA32_APERF: u32 = 0xe8;
419pub const MSR_IA32_THERM_CONTROL: u32 = 0x19a;
420pub const MSR_IA32_THERM_INTERRUPT: u32 = 0x19b;
421pub const MSR_IA32_THERM_STATUS: u32 = 0x19c;
422pub const MSR_THERM2_CTL: u32 = 0x19d;
423pub const MSR_THERM2_CTL_TM_SELECT: u32 = 0x10000;
424pub const MSR_IA32_MISC_ENABLE: u32 = 0x1a0;
425pub const MSR_IA32_TEMPERATURE_TARGET: u32 = 0x1a2;
426pub const MSR_MISC_FEATURE_CONTROL: u32 = 0x1a4;
427pub const MSR_MISC_PWR_MGMT: u32 = 0x1aa;
428pub const MSR_IA32_ENERGY_PERF_BIAS: u32 = 0x1b0;
429pub const MSR_IA32_PACKAGE_THERM_STATUS: u32 = 0x1b1;
430pub const MSR_IA32_PACKAGE_THERM_INTERRUPT: u32 = 0x1b2;
431pub const MSR_IA32_MISC_ENABLE_FAST_STRING_BIT: u32 = 0x0;
432pub const MSR_IA32_MISC_ENABLE_FAST_STRING: u32 = 0x1;
433pub const MSR_IA32_MISC_ENABLE_TCC_BIT: u32 = 0x1;
434pub const MSR_IA32_MISC_ENABLE_TCC: u32 = 0x2;
435pub const MSR_IA32_MISC_ENABLE_EMON_BIT: u32 = 0x7;
436pub const MSR_IA32_MISC_ENABLE_EMON: u32 = 0x80;
437pub const MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT: u32 = 0xb;
438pub const MSR_IA32_MISC_ENABLE_BTS_UNAVAIL: u32 = 0x800;
439pub const MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT: u32 = 0xc;
440pub const MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL: u32 = 0x1000;
441pub const MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT: u32 = 0x10;
442pub const MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP: u32 = 0x10000;
443pub const MSR_IA32_MISC_ENABLE_MWAIT_BIT: u32 = 0x12;
444pub const MSR_IA32_MISC_ENABLE_MWAIT: u32 = 0x40000;
445pub const MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT: u32 = 0x16;
446pub const MSR_IA32_MISC_ENABLE_LIMIT_CPUID: u32 = 0x400000;
447pub const MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT: u32 = 0x17;
448pub const MSR_IA32_MISC_ENABLE_XTPR_DISABLE: u32 = 0x800000;
449pub const MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT: u32 = 0x22;
450pub const MSR_IA32_MISC_ENABLE_XD_DISABLE: u64 = 0x400000000;
451pub const MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT: u32 = 0x2;
452pub const MSR_IA32_MISC_ENABLE_X87_COMPAT: u32 = 0x4;
453pub const MSR_IA32_MISC_ENABLE_TM1_BIT: u32 = 0x3;
454pub const MSR_IA32_MISC_ENABLE_TM1: u32 = 0x8;
455pub const MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT: u32 = 0x4;
456pub const MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE: u32 = 0x10;
457pub const MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT: u32 = 0x6;
458pub const MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE: u32 = 0x40;
459pub const MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT: u32 = 0x8;
460pub const MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK: u32 = 0x100;
461pub const MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT: u32 = 0x9;
462pub const MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE: u32 = 0x200;
463pub const MSR_IA32_MISC_ENABLE_FERR_BIT: u32 = 0xa;
464pub const MSR_IA32_MISC_ENABLE_FERR: u32 = 0x400;
465pub const MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT: u32 = 0xa;
466pub const MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX: u32 = 0x400;
467pub const MSR_IA32_MISC_ENABLE_TM2_BIT: u32 = 0xd;
468pub const MSR_IA32_MISC_ENABLE_TM2: u32 = 0x2000;
469pub const MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT: u32 = 0x13;
470pub const MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE: u32 = 0x80000;
471pub const MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT: u32 = 0x14;
472pub const MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK: u32 = 0x100000;
473pub const MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT: u32 = 0x18;
474pub const MSR_IA32_MISC_ENABLE_L1D_CONTEXT: u32 = 0x1000000;
475pub const MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT: u32 = 0x25;
476pub const MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE: u64 = 0x2000000000;
477pub const MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT: u32 = 0x26;
478pub const MSR_IA32_MISC_ENABLE_TURBO_DISABLE: u64 = 0x4000000000;
479pub const MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT: u32 = 0x27;
480pub const MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE: u64 = 0x8000000000;
481pub const MSR_MISC_FEATURES_ENABLES: u32 = 0x140;
482pub const MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT: u32 = 0x0;
483pub const MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT: u32 = 0x1;
484pub const MSR_IA32_TSC_DEADLINE: u32 = 0x6e0;
485pub const MSR_TSX_FORCE_ABORT: u32 = 0x10f;
486pub const MSR_TFA_RTM_FORCE_ABORT_BIT: u32 = 0x0;
487pub const MSR_TFA_TSX_CPUID_CLEAR_BIT: u32 = 0x1;
488pub const MSR_TFA_SDV_ENABLE_RTM_BIT: u32 = 0x2;
489pub const MSR_IA32_MCG_EAX: u32 = 0x180;
490pub const MSR_IA32_MCG_EBX: u32 = 0x181;
491pub const MSR_IA32_MCG_ECX: u32 = 0x182;
492pub const MSR_IA32_MCG_EDX: u32 = 0x183;
493pub const MSR_IA32_MCG_ESI: u32 = 0x184;
494pub const MSR_IA32_MCG_EDI: u32 = 0x185;
495pub const MSR_IA32_MCG_EBP: u32 = 0x186;
496pub const MSR_IA32_MCG_ESP: u32 = 0x187;
497pub const MSR_IA32_MCG_EFLAGS: u32 = 0x188;
498pub const MSR_IA32_MCG_EIP: u32 = 0x189;
499pub const MSR_IA32_MCG_RESERVED: u32 = 0x18a;
500pub const MSR_P4_BPU_PERFCTR0: u32 = 0x300;
501pub const MSR_P4_BPU_PERFCTR1: u32 = 0x301;
502pub const MSR_P4_BPU_PERFCTR2: u32 = 0x302;
503pub const MSR_P4_BPU_PERFCTR3: u32 = 0x303;
504pub const MSR_P4_MS_PERFCTR0: u32 = 0x304;
505pub const MSR_P4_MS_PERFCTR1: u32 = 0x305;
506pub const MSR_P4_MS_PERFCTR2: u32 = 0x306;
507pub const MSR_P4_MS_PERFCTR3: u32 = 0x307;
508pub const MSR_P4_FLAME_PERFCTR0: u32 = 0x308;
509pub const MSR_P4_FLAME_PERFCTR1: u32 = 0x309;
510pub const MSR_P4_FLAME_PERFCTR2: u32 = 0x30a;
511pub const MSR_P4_FLAME_PERFCTR3: u32 = 0x30b;
512pub const MSR_P4_IQ_PERFCTR0: u32 = 0x30c;
513pub const MSR_P4_IQ_PERFCTR1: u32 = 0x30d;
514pub const MSR_P4_IQ_PERFCTR2: u32 = 0x30e;
515pub const MSR_P4_IQ_PERFCTR3: u32 = 0x30f;
516pub const MSR_P4_IQ_PERFCTR4: u32 = 0x310;
517pub const MSR_P4_IQ_PERFCTR5: u32 = 0x311;
518pub const MSR_P4_BPU_CCCR0: u32 = 0x360;
519pub const MSR_P4_BPU_CCCR1: u32 = 0x361;
520pub const MSR_P4_BPU_CCCR2: u32 = 0x362;
521pub const MSR_P4_BPU_CCCR3: u32 = 0x363;
522pub const MSR_P4_MS_CCCR0: u32 = 0x364;
523pub const MSR_P4_MS_CCCR1: u32 = 0x365;
524pub const MSR_P4_MS_CCCR2: u32 = 0x366;
525pub const MSR_P4_MS_CCCR3: u32 = 0x367;
526pub const MSR_P4_FLAME_CCCR0: u32 = 0x368;
527pub const MSR_P4_FLAME_CCCR1: u32 = 0x369;
528pub const MSR_P4_FLAME_CCCR2: u32 = 0x36a;
529pub const MSR_P4_FLAME_CCCR3: u32 = 0x36b;
530pub const MSR_P4_IQ_CCCR0: u32 = 0x36c;
531pub const MSR_P4_IQ_CCCR1: u32 = 0x36d;
532pub const MSR_P4_IQ_CCCR2: u32 = 0x36e;
533pub const MSR_P4_IQ_CCCR3: u32 = 0x36f;
534pub const MSR_P4_IQ_CCCR4: u32 = 0x370;
535pub const MSR_P4_IQ_CCCR5: u32 = 0x371;
536pub const MSR_P4_ALF_ESCR0: u32 = 0x3ca;
537pub const MSR_P4_ALF_ESCR1: u32 = 0x3cb;
538pub const MSR_P4_BPU_ESCR0: u32 = 0x3b2;
539pub const MSR_P4_BPU_ESCR1: u32 = 0x3b3;
540pub const MSR_P4_BSU_ESCR0: u32 = 0x3a0;
541pub const MSR_P4_BSU_ESCR1: u32 = 0x3a1;
542pub const MSR_P4_CRU_ESCR0: u32 = 0x3b8;
543pub const MSR_P4_CRU_ESCR1: u32 = 0x3b9;
544pub const MSR_P4_CRU_ESCR2: u32 = 0x3cc;
545pub const MSR_P4_CRU_ESCR3: u32 = 0x3cd;
546pub const MSR_P4_CRU_ESCR4: u32 = 0x3e0;
547pub const MSR_P4_CRU_ESCR5: u32 = 0x3e1;
548pub const MSR_P4_DAC_ESCR0: u32 = 0x3a8;
549pub const MSR_P4_DAC_ESCR1: u32 = 0x3a9;
550pub const MSR_P4_FIRM_ESCR0: u32 = 0x3a4;
551pub const MSR_P4_FIRM_ESCR1: u32 = 0x3a5;
552pub const MSR_P4_FLAME_ESCR0: u32 = 0x3a6;
553pub const MSR_P4_FLAME_ESCR1: u32 = 0x3a7;
554pub const MSR_P4_FSB_ESCR0: u32 = 0x3a2;
555pub const MSR_P4_FSB_ESCR1: u32 = 0x3a3;
556pub const MSR_P4_IQ_ESCR0: u32 = 0x3ba;
557pub const MSR_P4_IQ_ESCR1: u32 = 0x3bb;
558pub const MSR_P4_IS_ESCR0: u32 = 0x3b4;
559pub const MSR_P4_IS_ESCR1: u32 = 0x3b5;
560pub const MSR_P4_ITLB_ESCR0: u32 = 0x3b6;
561pub const MSR_P4_ITLB_ESCR1: u32 = 0x3b7;
562pub const MSR_P4_IX_ESCR0: u32 = 0x3c8;
563pub const MSR_P4_IX_ESCR1: u32 = 0x3c9;
564pub const MSR_P4_MOB_ESCR0: u32 = 0x3aa;
565pub const MSR_P4_MOB_ESCR1: u32 = 0x3ab;
566pub const MSR_P4_MS_ESCR0: u32 = 0x3c0;
567pub const MSR_P4_MS_ESCR1: u32 = 0x3c1;
568pub const MSR_P4_PMH_ESCR0: u32 = 0x3ac;
569pub const MSR_P4_PMH_ESCR1: u32 = 0x3ad;
570pub const MSR_P4_RAT_ESCR0: u32 = 0x3bc;
571pub const MSR_P4_RAT_ESCR1: u32 = 0x3bd;
572pub const MSR_P4_SAAT_ESCR0: u32 = 0x3ae;
573pub const MSR_P4_SAAT_ESCR1: u32 = 0x3af;
574pub const MSR_P4_SSU_ESCR0: u32 = 0x3be;
575pub const MSR_P4_SSU_ESCR1: u32 = 0x3bf;
576pub const MSR_P4_TBPU_ESCR0: u32 = 0x3c2;
577pub const MSR_P4_TBPU_ESCR1: u32 = 0x3c3;
578pub const MSR_P4_TC_ESCR0: u32 = 0x3c4;
579pub const MSR_P4_TC_ESCR1: u32 = 0x3c5;
580pub const MSR_P4_U2L_ESCR0: u32 = 0x3b0;
581pub const MSR_P4_U2L_ESCR1: u32 = 0x3b1;
582pub const MSR_P4_PEBS_MATRIX_VERT: u32 = 0x3f2;
583pub const MSR_CORE_PERF_FIXED_CTR0: u32 = 0x309;
584pub const MSR_CORE_PERF_FIXED_CTR1: u32 = 0x30a;
585pub const MSR_CORE_PERF_FIXED_CTR2: u32 = 0x30b;
586pub const MSR_CORE_PERF_FIXED_CTR3: u32 = 0x30c;
587pub const MSR_CORE_PERF_FIXED_CTR_CTRL: u32 = 0x38d;
588pub const MSR_CORE_PERF_GLOBAL_STATUS: u32 = 0x38e;
589pub const MSR_CORE_PERF_GLOBAL_CTRL: u32 = 0x38f;
590pub const MSR_CORE_PERF_GLOBAL_OVF_CTRL: u32 = 0x390;
591pub const MSR_PERF_METRICS: u32 = 0x329;
592pub const MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT: u32 = 0x37;
593pub const MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI: u64 = 0x80000000000000;
594pub const MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT: u32 = 0x3e;
595pub const MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF: u64 = 0x4000000000000000;
596pub const MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT: u32 = 0x3f;
597pub const MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD: i64 = -9223372036854775808;
598pub const MSR_GEODE_BUSCONT_CONF0: u32 = 0x1900;
599pub const MSR_IA32_VMX_BASIC: u32 = 0x480;
600pub const MSR_IA32_VMX_PINBASED_CTLS: u32 = 0x481;
601pub const MSR_IA32_VMX_PROCBASED_CTLS: u32 = 0x482;
602pub const MSR_IA32_VMX_EXIT_CTLS: u32 = 0x483;
603pub const MSR_IA32_VMX_ENTRY_CTLS: u32 = 0x484;
604pub const MSR_IA32_VMX_MISC: u32 = 0x485;
605pub const MSR_IA32_VMX_CR0_FIXED0: u32 = 0x486;
606pub const MSR_IA32_VMX_CR0_FIXED1: u32 = 0x487;
607pub const MSR_IA32_VMX_CR4_FIXED0: u32 = 0x488;
608pub const MSR_IA32_VMX_CR4_FIXED1: u32 = 0x489;
609pub const MSR_IA32_VMX_VMCS_ENUM: u32 = 0x48a;
610pub const MSR_IA32_VMX_PROCBASED_CTLS2: u32 = 0x48b;
611pub const MSR_IA32_VMX_EPT_VPID_CAP: u32 = 0x48c;
612pub const MSR_IA32_VMX_TRUE_PINBASED_CTLS: u32 = 0x48d;
613pub const MSR_IA32_VMX_TRUE_PROCBASED_CTLS: u32 = 0x48e;
614pub const MSR_IA32_VMX_TRUE_EXIT_CTLS: u32 = 0x48f;
615pub const MSR_IA32_VMX_TRUE_ENTRY_CTLS: u32 = 0x490;
616pub const MSR_IA32_VMX_VMFUNC: u32 = 0x491;
617pub const MSR_IA32_VMX_PROCBASED_CTLS3: u32 = 0x492;
618pub const MSR_IA32_L3_QOS_CFG: u32 = 0xc81;
619pub const MSR_IA32_L2_QOS_CFG: u32 = 0xc82;
620pub const MSR_IA32_QM_EVTSEL: u32 = 0xc8d;
621pub const MSR_IA32_QM_CTR: u32 = 0xc8e;
622pub const MSR_IA32_PQR_ASSOC: u32 = 0xc8f;
623pub const MSR_IA32_L3_CBM_BASE: u32 = 0xc90;
624pub const MSR_RMID_SNC_CONFIG: u32 = 0xca0;
625pub const MSR_IA32_L2_CBM_BASE: u32 = 0xd10;
626pub const MSR_IA32_MBA_THRTL_BASE: u32 = 0xd50;
627pub const MSR_IA32_MBA_BW_BASE: u32 = 0xc0000200;
628pub const MSR_IA32_SMBA_BW_BASE: u32 = 0xc0000280;
629pub const MSR_IA32_EVT_CFG_BASE: u32 = 0xc0000400;
630pub const MSR_VM_CR: u32 = 0xc0010114;
631pub const MSR_VM_IGNNE: u32 = 0xc0010115;
632pub const MSR_VM_HSAVE_PA: u32 = 0xc0010117;
633pub const MSR_IA32_HW_FEEDBACK_PTR: u32 = 0x17d0;
634pub const MSR_IA32_HW_FEEDBACK_CONFIG: u32 = 0x17d1;
635pub const MSR_IA32_XAPIC_DISABLE_STATUS: u32 = 0xbd;