vmm/cpu_config/x86_64/static_cpu_templates/t2.rs
1// Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved.
2// SPDX-License-Identifier: Apache-2.0
3
4use crate::cpu_config::templates::{CustomCpuTemplate, RegisterValueFilter};
5use crate::cpu_config::x86_64::cpuid::KvmCpuidFlags;
6use crate::cpu_config::x86_64::custom_cpu_template::{
7 CpuidLeafModifier, CpuidRegister, CpuidRegisterModifier,
8};
9
10/// T2 template
11///
12/// Mask CPUID to make exposed CPU features as close as possbile to AWS T2 instance.
13///
14/// CPUID dump taken in t2.micro on 2023-06-15:
15/// =====
16/// $ cpuid -1 -r
17/// Disclaimer: cpuid may not support decoding of all cpuid registers.
18/// CPU:
19/// 0x00000000 0x00: eax=0x0000000d ebx=0x756e6547 ecx=0x6c65746e edx=0x49656e69
20/// 0x00000001 0x00: eax=0x000306f2 ebx=0x00010800 ecx=0xfffa3203 edx=0x178bfbff
21/// 0x00000002 0x00: eax=0x76036301 ebx=0x00f0b5ff ecx=0x00000000 edx=0x00c10000
22/// 0x00000003 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
23/// 0x00000004 0x00: eax=0x00004121 ebx=0x01c0003f ecx=0x0000003f edx=0x00000000
24/// 0x00000004 0x01: eax=0x00004122 ebx=0x01c0003f ecx=0x0000003f edx=0x00000000
25/// 0x00000004 0x02: eax=0x00004143 ebx=0x01c0003f ecx=0x000001ff edx=0x00000000
26/// 0x00000004 0x03: eax=0x0007c163 ebx=0x04c0003f ecx=0x00005fff edx=0x00000006
27/// 0x00000005 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
28/// 0x00000006 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
29/// 0x00000007 0x00: eax=0x00000000 ebx=0x000007a9 ecx=0x00000000 edx=0x00000000
30/// 0x00000008 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
31/// 0x00000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
32/// 0x0000000a 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
33/// 0x0000000b 0x00: eax=0x00000001 ebx=0x00000001 ecx=0x00000100 edx=0x00000000
34/// 0x0000000b 0x01: eax=0x00000005 ebx=0x00000001 ecx=0x00000201 edx=0x00000000
35/// 0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
36/// 0x0000000d 0x00: eax=0x00000007 ebx=0x00000340 ecx=0x00000340 edx=0x00000000
37/// 0x0000000d 0x01: eax=0x00000001 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
38/// 0x0000000d 0x02: eax=0x00000100 ebx=0x00000240 ecx=0x00000000 edx=0x00000000
39/// 0x40000000 0x00: eax=0x40000005 ebx=0x566e6558 ecx=0x65584d4d edx=0x4d4d566e
40/// 0x40000001 0x00: eax=0x0004000b ebx=0x00000000 ecx=0x00000000 edx=0x00000000
41/// 0x40000002 0x00: eax=0x00000001 ebx=0x40000000 ecx=0x00000000 edx=0x00000000
42/// 0x40000003 0x00: eax=0x00000006 ebx=0x00000002 ecx=0x00249f0a edx=0x00000001
43/// 0x40000003 0x02: eax=0x9b842c23 ebx=0x007c8980 ecx=0xd5551b14 edx=0xffffffff
44/// 0x40000004 0x00: eax=0x0000001c ebx=0x00000000 ecx=0x0000762b edx=0x00000000
45/// 0x40000005 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
46/// 0x80000000 0x00: eax=0x80000008 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
47/// 0x80000001 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000021 edx=0x28100800
48/// 0x80000002 0x00: eax=0x65746e49 ebx=0x2952286c ecx=0x6f655820 edx=0x2952286e
49/// 0x80000003 0x00: eax=0x55504320 ebx=0x2d354520 ecx=0x36373632 edx=0x20337620
50/// 0x80000004 0x00: eax=0x2e322040 ebx=0x48473034 ecx=0x0000007a edx=0x00000000
51/// 0x80000005 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
52/// 0x80000006 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x01006040 edx=0x00000000
53/// 0x80000007 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
54/// 0x80000008 0x00: eax=0x0000302e ebx=0x00000000 ecx=0x00000000 edx=0x00000000
55/// 0x80860000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
56/// 0xc0000000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
57/// =====
58///
59/// References:
60/// - Intel SDM: <https://cdrdv2.intel.com/v1/dl/getContent/671200>
61#[allow(clippy::unusual_byte_groupings)]
62pub fn t2() -> CustomCpuTemplate {
63 CustomCpuTemplate {
64 cpuid_modifiers: vec![
65 CpuidLeafModifier {
66 leaf: 0x1,
67 subleaf: 0x0,
68 flags: KvmCpuidFlags(0),
69 modifiers: vec![
70 // EAX: Version Information
71 // - Bits 03-00: Stepping ID.
72 // - Bits 07-04: Model.
73 // - Bits 11-08: Family.
74 // - Bits 13-12: Processor Type.
75 // - Bits 19-16: Extended Model ID.
76 // - Bits 27-20: Extended Family ID.
77 CpuidRegisterModifier {
78 register: CpuidRegister::Eax,
79 bitmap: RegisterValueFilter {
80 filter: 0b0000_11111111_1111_00_11_1111_1111_1111,
81 value: 0b0000_00000000_0011_00_00_0110_1111_0010,
82 },
83 },
84 // ECX: Feature Information
85 // - Bit 02: DTES64
86 // - Bit 03: MONITOR
87 // - Bit 04: DS-CPL
88 // - Bit 05: VMX
89 // - Bit 06: SMX
90 // - Bit 07: EIST
91 // - Bit 08: TM2
92 // - Bit 10: CNXT-ID
93 // - Bit 11: SDBG
94 // - Bit 14: xTPR Update Control
95 // - Bit 15: PDCM
96 // - Bit 18: DCA
97 CpuidRegisterModifier {
98 register: CpuidRegister::Ecx,
99 bitmap: RegisterValueFilter {
100 filter: 0b0000_0000_0000_0100_1100_1101_1111_1100,
101 value: 0b0000_0000_0000_0000_0000_0000_0000_0000,
102 },
103 },
104 // EDX: Feature Information
105 // - Bit 07: MCE
106 // - Bit 12: MTRR
107 // - Bit 18: PSN
108 // - Bit 21: DS
109 // - Bit 22: ACPI
110 // - Bit 27: SS
111 // - Bit 29: TM
112 // - Bit 30: IA-64 (deprecated) https://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-vol-4-manual.pdf
113 // - Bit 31: PBE
114 CpuidRegisterModifier {
115 register: CpuidRegister::Edx,
116 bitmap: RegisterValueFilter {
117 filter: 0b1110_1000_0110_0100_0001_0000_1000_0000,
118 value: 0b0000_0000_0000_0000_0001_0000_1000_0000,
119 },
120 },
121 ],
122 },
123 CpuidLeafModifier {
124 leaf: 0x7,
125 subleaf: 0x0,
126 flags: KvmCpuidFlags(1),
127 modifiers: vec![
128 // EBX:
129 // - Bit 02: SGX
130 // - Bit 04: HLE
131 // - Bit 09: Enhanced REP MOVSB/STOSB
132 // - Bit 11: RTM
133 // - Bit 12: RDT-M
134 // - Bit 14: MPX
135 // - Bit 15: RDT-A
136 // - Bit 16: AVX512F
137 // - Bit 17: AVX512DQ
138 // - Bit 18: RDSEED
139 // - Bit 19: ADX
140 // - Bit 21: AVX512_IFMA
141 // - Bit 22: PCOMMIT (deprecated) https://www.intel.com/content/www/us/en/developer/articles/technical/deprecate-pcommit-instruction.html
142 // - Bit 23: CLFLUSHOPT
143 // - Bit 24: CLWB
144 // - Bit 25: Intel Processor Trace
145 // - Bit 26: AVX512PF
146 // - Bit 27: AVX512ER
147 // - Bit 28: AVX512CD
148 // - Bit 29: SHA
149 // - Bit 30: AVX512BW
150 // - Bit 31: AVX512VL
151 CpuidRegisterModifier {
152 register: CpuidRegister::Ebx,
153 bitmap: RegisterValueFilter {
154 filter: 0b1111_1111_1110_1111_1101_1010_0001_0100,
155 value: 0b0000_0000_0000_0000_0000_0010_0000_0000,
156 },
157 },
158 // ECX:
159 // - Bit 01: AVX512_VBMI
160 // - Bit 02: UMIP
161 // - Bit 03: PKU
162 // - Bit 04: OSPKE
163 // - Bit 06: AVX512_VBMI2
164 // - Bit 08: GFNI
165 // - Bit 09: VAES
166 // - Bit 10: VPCLMULQDQ
167 // - Bit 11: AVX512_VNNI
168 // - Bit 12: AVX512_BITALG
169 // - Bit 14: AVX512_VPOPCNTDQ
170 // - Bit 16: LA57
171 // - Bit 22: RDPID
172 // - Bit 30: SGX_LC
173 CpuidRegisterModifier {
174 register: CpuidRegister::Ecx,
175 bitmap: RegisterValueFilter {
176 filter: 0b0100_0000_0100_0001_0101_1111_0101_1110,
177 value: 0b0000_0000_0000_0000_0000_0000_0000_0000,
178 },
179 },
180 // EDX:
181 // - Bit 02: AVX512_4VNNIW
182 // - Bit 03: AVX512_4FMAPS
183 // - Bit 04: Fast Short REP MOV
184 // - Bit 08: AVX512_VP2INTERSECT
185 CpuidRegisterModifier {
186 register: CpuidRegister::Edx,
187 bitmap: RegisterValueFilter {
188 filter: 0b0000_0000_0000_0000_0000_0001_0001_1100,
189 value: 0b0000_0000_0000_0000_0000_0000_0000_0000,
190 },
191 },
192 ],
193 },
194 CpuidLeafModifier {
195 leaf: 0xd,
196 subleaf: 0x0,
197 flags: KvmCpuidFlags(1),
198 modifiers: vec![
199 // EAX:
200 // - Bits 04-03: MPX state
201 // - Bits 07-05: AVX-512 state
202 // - Bit 09: PKRU state
203 CpuidRegisterModifier {
204 register: CpuidRegister::Eax,
205 bitmap: RegisterValueFilter {
206 filter: 0b0000_0000_0000_0000_0000_00_1_0_111_11_000,
207 value: 0b0000_0000_0000_0000_0000_00_0_0_000_00_000,
208 },
209 },
210 ],
211 },
212 CpuidLeafModifier {
213 leaf: 0xd,
214 subleaf: 0x1,
215 flags: KvmCpuidFlags(1),
216 modifiers: vec![
217 // EAX:
218 // - Bit 01: Supports XSAVEC and the compacted form of XRSTOR
219 // - Bit 02: Supports XGETBV
220 // - Bit 03: Supports XSAVES/XRSTORS and IA32_XSS
221 CpuidRegisterModifier {
222 register: CpuidRegister::Eax,
223 bitmap: RegisterValueFilter {
224 filter: 0b0000_0000_0000_0000_0000_0000_0000_1110,
225 value: 0b0000_0000_0000_0000_0000_0000_0000_0000,
226 },
227 },
228 ],
229 },
230 CpuidLeafModifier {
231 leaf: 0x80000001,
232 subleaf: 0x0,
233 flags: KvmCpuidFlags(0),
234 modifiers: vec![
235 // ECX:
236 // - Bit 08: PREFETCHW
237 // - Bit 29: MONITORX and MWAITX
238 CpuidRegisterModifier {
239 register: CpuidRegister::Ecx,
240 bitmap: RegisterValueFilter {
241 filter: 0b0010_0000_0000_0000_0000_0001_0000_0000,
242 value: 0b0000_0000_0000_0000_0000_0000_0000_0000,
243 },
244 },
245 // EDX:
246 // - Bit 26: 1-GByte pages
247 CpuidRegisterModifier {
248 register: CpuidRegister::Edx,
249 bitmap: RegisterValueFilter {
250 filter: 0b0000_0100_0000_0000_0000_0000_0000_0000,
251 value: 0b0000_0000_0000_0000_0000_0000_0000_0000,
252 },
253 },
254 ],
255 },
256 CpuidLeafModifier {
257 leaf: 0x80000008,
258 subleaf: 0x0,
259 flags: KvmCpuidFlags(0),
260 modifiers: vec![
261 // EBX:
262 // - Bit 09: WBNOINVD
263 CpuidRegisterModifier {
264 register: CpuidRegister::Ebx,
265 bitmap: RegisterValueFilter {
266 filter: 0b0000_0000_0000_0000_0000_0010_0000_0000,
267 value: 0b0000_0000_0000_0000_0000_0000_0000_0000,
268 },
269 },
270 ],
271 },
272 ],
273 msr_modifiers: vec![],
274 ..Default::default()
275 }
276}